ml_switcheroo.compiler.backends.rdna.synthesizer¶

RDNA Synthesizer and Registry Backend.

This module provides the “Middle-End” logic for the RDNA compiler pipeline. It bridges the gap between high-level Abstract Logic (LogicalGraphs) and low-level Physical Assembly (Instruction nodes/Registers).

It contains: 1. RegisterAllocator: A dual-pool allocator managing Scalar (SGPR) and

Vector (VGPR) register files independently.

RdnaSynthesizer: - Target Transformation (`from_graph`): Converts topological logical graphs

into a linear list of RDNA instructions.
- Source Transformation (`to_python`): Converts RDNA AST nodes back into Python LibCST nodes for high-level analysis or documentation.
RdnaBackend: The CompilerBackend adapter for the Registry, including header generation.

Attributes¶

`MAX_VGPR`
`MAX_SGPR`

Classes¶

`RegisterAllocator`	Manages the mapping between symbolic variable names and physical registers.
`RdnaSynthesizer`	Bidirectional transpiler component for RDNA ISA.
`RdnaBackend`	Compiler Backend implementation for AMD RDNA.

Module Contents¶

ml_switcheroo.compiler.backends.rdna.synthesizer.MAX_VGPR = 256¶

ml_switcheroo.compiler.backends.rdna.synthesizer.MAX_SGPR = 106¶

class ml_switcheroo.compiler.backends.rdna.synthesizer.RegisterAllocator[source]¶

Manages the mapping between symbolic variable names and physical registers. Maintains separate accounting for Scalar (SGPR) and Vector (VGPR) files.

get_vector_register(var_name: str) → ml_switcheroo.compiler.frontends.rdna.nodes.VGPR[source]¶: Retrieves or allocates a Vector register (VGPR) for a symbolic variable.

get_scalar_register(var_name: str) → ml_switcheroo.compiler.frontends.rdna.nodes.SGPR[source]¶: Retrieves or allocates a Scalar register (SGPR) for a symbolic variable.

allocate_vector_temp() → ml_switcheroo.compiler.frontends.rdna.nodes.VGPR[source]¶: Allocates an anonymous temporary VGPR.

allocate_scalar_temp() → ml_switcheroo.compiler.frontends.rdna.nodes.SGPR[source]¶: Allocates an anonymous temporary SGPR.

reset() → None[source]¶: Resets all allocation state.

class ml_switcheroo.compiler.backends.rdna.synthesizer.RdnaSynthesizer(semantics: ml_switcheroo.semantics.manager.SemanticsManager)[source]¶

Bidirectional transpiler component for RDNA ISA.

semantics¶

allocator¶

macro_registry: Dict[str, Callable]¶

from_graph(graph: ml_switcheroo.compiler.ir.LogicalGraph) → List[ml_switcheroo.compiler.frontends.rdna.nodes.RdnaNode][source]¶: Converts a LogicalGraph into a list of RDNA AST nodes.

to_python(rdna_nodes: List[ml_switcheroo.compiler.frontends.rdna.nodes.RdnaNode]) → libcst.Module[source]¶: Converts RDNA AST nodes into a Python source structure representation.

class ml_switcheroo.compiler.backends.rdna.synthesizer.RdnaBackend(semantics: ml_switcheroo.semantics.manager.SemanticsManager | None = None)[source]¶

Bases: ml_switcheroo.compiler.backend.CompilerBackend

Compiler Backend implementation for AMD RDNA. Orchestrates the synthesis (Graph -> AST) and emission (AST -> Text).

synthesizer¶

emitter¶

target_arch = 'gfx1030'¶

compile(graph: ml_switcheroo.compiler.ir.LogicalGraph) → str[source]¶

Compiles LogicalGraph to RDNA Assembly string.

Parameters:: graph – The intermediate representation.
Returns:: The RDNA code.
Return type:: str